The present invention relates generally to integrated circuit (chip) design, and more specifically, to synthesis of a logical chip design to a physical design.
Timing closure in VLSI design is an optimization process to meet the target timing performance while satisfying geometric constraints of a design. In modern design flows, this concept is extended to design closure by including power, thermal and manufacturability constraints that become more important as technology pursues decreased component sizing. Nonetheless, timing constrains contribute significantly to the quality of a design. Timing closure itself includes several optimizations such as placement, routing, sizing transistors or gates, buffer insertion and sometimes logic restructuring. For instance, critical paths between latches and/or gates affect the overall timing closure. These critical paths can deviate or meander from the desired design path thereby increasing path delays and overall timing closure.